This invention is in the field of electronically programmable semiconductor memories of the EPROM or EEPROM type.
Non-volatile, programmable memory storage is provided in CMOS technology through the conventional EPROM (electrically programmable ROM) and EEPROM (electrically erasable PROM) structures. Examples of these structures are given by D. G. Ong in Chapter 9 of MODERN MOS TECHNOLOGY, McGraw-Hill, 1984, at pages 212-216. Each device incorporates a conventional CMOS (complementary metal-oxide silicon) structure in which an intrinsically p-conducting substrate has diffused n-type source and drain regions, between which lies a channel region. A control gate is formed on the semiconductor substrate and spans the channel region between the source and drain regions. The gate is electrically insulated from the substrate by a gate oxide sandwiched between the gate and the substrate surface.
The EPROM structure includes a floating gate located between the channel region and the control gate, and insulated from the control gate by a first layer of gate oxide and from the channel region by a second layer of gate oxide. This EPROM cell is "written" by application of a relatively high positive voltage to the drain region and a higher relatively positive voltage to the control gate. The drain voltage accelerates electrons in the channel region, while the high gate voltage provides channel region electrons with enough energy to be injected across the second gate oxide layer separating the floating gate from the channel. Writing collects or captures channel electrons in the floating gate, which raises the voltage threshold required to make the channel region conductive above that when the floating gate has no channel electrons. Such a cell is referred to as a "written" cell. Conventional CMOS circuitry references a "written" cell as storage of a digital value of "1". An unwritten cell is considered to indicate a data storage value of a digital "0".
In the typical EEPROM cell, a floating gate spans the channel region and extends over the drain region. In the channel region, the oxide layer insulating the floating gate from the substrate surface has a thickness corresponding to the thickness of an EPROM gate oxide layer. However, the gate oxide layer under the portion of the floating gate overlying the drain region is made substantially thinner. The thin oxide layer is referred to as a "tunnel oxide layer" to denote the tunneling mechanism by which electrons are injected through the layer into the floating gate from the drain region and extracted from the floating gate by the drain region, according to the cell biasing. See Ong at pages 213 and 216.
As is known, relatively high voltages and relatively long writing times are required by prior art EPROM structure in order to "write" a cell. Further, the classical EPROM structure requires extraordinary methods to erase a cell. For example, the prior art teaches EPROM erasure by exposure of the memory cell to UV light for a long period of time. The EEPROM structure was developed in an effort to provide relatively faster writing at relatively lower voltages, together with an ability to erase a written cell in situ.
The thrust of development in CMOS non-volatile memory cell technology has been to reduce voltage levels required for operating these devices, thereby enhancing the efficiency of cell operation, and to reduce write and erase times.